Cadence Design Systems, Inc. (Nasdaq: CDNS) today unveiled its third-generation 112G long-reach (112G-LR) SerDes IP on TSMC’s N5 process for hyperscale ASICs, artificial intelligence/machine learning (AI/ML) accelerators, and switch fabric systems on chip (SoCs). The Cadence® 112G-LR PAM4 SerDes IP on TSMC’s N5 process delivers the power, performance and area (PPA) efficiency required to build the high-bandwidth and high-reliability products for next-generation cloud data centers. The innovative architecture offers 25% power savings, 40% area reduction and better design margins over the second-generation architecture, satisfying the increasing needs for higher performance and power efficiency in today’s data centers.
Cadence Accelerates Cloud Hyperscale Infrastructure with Third-Generation 112G-LR SerDes IP on TSMC's N5 Process
May 24, 2021
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