At the IEEE International Electron Devices Meeting (IEDM) in San Francisco, TSMC unveiled detailed information about its advanced 2nm (N2) process technology. The N2 process boasts a 15% performance boost compared to its predecessor, with power consumption reduced by up to 30%, thereby significantly enhancing efficiency.
Further advancements include a 1.15-fold increase in transistor density, achieved through the integration of gate-all-around (GAA) nanosheet transistors and N2 NanoFlex technology. This innovation allows manufacturers to integrate varied logic units within minimal space, optimizing process performance. The price of N2 process wafers is expected to exceed that of the 3nm process by over 10%.
