- Marvell Technology (MRVL, Financial) introduces a cutting-edge multi-die packaging platform for AI accelerators.
- The platform supports 2.8x larger multi-chip accelerator designs compared to single-die implementations.
- Collaboration with all four top hyperscalers aims to develop custom XPUs and CPUs for optimized cloud and AI infrastructure.
Marvell Technology, Inc. (MRVL) has announced the launch of an innovative multi-die packaging platform designed to enhance AI infrastructure semiconductor solutions. The new platform enables multi-chip accelerator designs to be 2.8 times larger than conventional single-die implementations. A key component of this advancement is the novel redistribution layer (RDL) interposer, which integrates 1390 mm² of silicon and four HBM3/3E memory stacks.
This advanced packaging platform offers several key benefits including improved die-to-die interconnect efficiency, reduced power consumption, and enhanced chiplet yields, ultimately lowering the product cost. The platform has already been production-qualified with a major hyperscaler and is currently ramping up in production. Additionally, it supports existing HBM3/HBM3E memory technologies and is being tested for future HBM4 designs.
Marvell is actively collaborating with all four top hyperscalers to develop custom XPUs, CPUs, and other devices targeted at optimizing cloud and AI infrastructure. The modular design of the RDL interposer not only reduces materials and costs but also increases chiplet yields by allowing the replacement of individual dies.
According to TechInsights, the market for chiplet processors is projected to grow by 31% annually, forecasting a revenue of $145 billion by 2030. This positions Marvell's cutting-edge packaging platform as a critical component in the evolution and adoption of chiplet architectures in the semiconductor industry.
