- Arteris (AIP, Financial) introduces Magillem Packaging, enhancing IP block and chiplet integration in semiconductor design.
- The software supports IEEE 1685-2022 standard, automating assembly processes to reduce time and errors.
- Partners Andes Technology and MIPS validate the product's potential to streamline SoC development.
Arteris, Inc. (AIP) has launched Magillem Packaging, a new software solution aimed at addressing the increasing complexity in semiconductor design by simplifying the integration of IP blocks and chiplets. This tool specifically targets the challenges faced in AI data centers and edge devices, helping engineering teams to efficiently organize and prepare numerous components for integration into chiplets or System-on-Chips (SoCs).
Magillem Packaging is based on the IEEE 1685 (IP-XACT) standard, enabling consistent and error-free generation of IP packages. Key features of the software include expansive IP reuse capabilities, correct-by-construction IEEE 1685-2022 generation, and scalable, automated IP packaging generation processes. It integrates seamlessly with industry tools and silicon IP, facilitating fast and efficient design workflows.
Endorsements from industry leaders such as Andes Technology and MIPS highlight the software's potential to streamline SoC development and accelerate the time-to-market for semiconductor companies. These partnerships underscore the strategic fit of Magillem Packaging within the industry, emphasizing its capacity to reduce design complexity and enhance engineering productivity.
With automation features that eliminate costly errors and delays, Magillem Packaging supports legacy versions of the IEEE 1685 standard, ensuring broad compatibility across varying design requirements. By simplifying the integration processes, Arteris positions itself as a pivotal player in the semiconductor design automation sector, providing valuable tools for chipmakers to maintain efficiency in their development cycles.
